1. Field of the Invention
The present invention relates to an echo generating apparatus for adding reverberative echo effect to an input signal and, more particularly, to an apparatus adapted for use in a system which gives reverberative echo effect to an audio signal outputted from a microphone.
2. Description of the Related Art
In an echo generating apparatus of the kind mentioned, its one fundamental component is an echo effect generator 1 which produces reverberative echo effect by delaying an input signal as shown in FIG. 1, and undesired noise is generally superposed on the output signal of the echo effect generator 1.
For example, clock noise and so forth are superposed in an analog type apparatus employing a bucket brigade device (BBD) as a signal delay means in the echo effect generator 1. Meanwhile in a digital type apparatus which employs an A-D converter, a memory circuit and a D-A converter, quantization noise and clock noise are superposed.
For the purpose of reducing such noise superposed on the output signal, it is customary to dispose a filter 2 (low-pass filter in most cases) in the following stage of the echo effect generator 1 so as to limit the band width by the filter.
FIGS. 2 and 3 show conventional analog type apparatus of the related art employing a BBD and so forth as a signal delay means in an echo effect generator.
The conventional example of FIG. 2 has a cyclic circuit configuration wherein an input signal is delayed while a BBD 16 is driven by-a clock generator 15, and the signal thus delayed is fed back to be processed by a calculator 17 for calculation with the input signal.
The conventional example of the related art shown in FIG. 3 has a transversal circuit configuration wherein an input signal is delayed sequentially while cascade-connected n-stage BBDs 26.sub.1 -26.sub.n are driven by a clock generator 25, and addition or subtraction is executed in a calculator 27 while the output signals of the n-stage BBDs 26.sub.1 -26.sub.n are multiplied by adequate coefficients respectively.
FIGS. 4 to 6 show conventional digital type apparatus of the related art employing an A-D converter, a memory circuit and a D-A converter as a signal delay means in an echo effect generator.
The conventional example of FIG. 4 has a cyclic circuit configuration wherein an input signal is delayed while an A-D converter 36, a memory circuit 37 and a D-A converter 38 are driven by a clock generator 35, and the signal thus delayed is fed back to be processed by a calculator 39 for calculation with the input signal.
The conventional example of the related art shown in FIG. 5 has a transversal circuit configuration wherein an input signal is delayed sequentially by cascade-connected n-stage memory circuits 47.sub.1 -47.sub.n, and addition or subtraction is executed in a calculator 49 while the output signals of the n-stage memory circuits 47.sub.1 -47.sub.n are multiplied by adequate coefficients respectively. And thereafter the calculated signals are converted into analog ones by a D-A converter 48.
In another conventional example of the related art shown in FIG. 6, output signals of n-stage memory circuits 57.sub.1 -57.sub.n are converted into analog ones by n-stage D-A converters 58.sub.1 -58.sub.n, and then addition or subtraction is executed in a calculator 59 while the analog signals are multiplied by adequate coefficients respectively.
In each of the conventional examples mentioned above, the noise amplitude in the output signal can be reduced by narrowing the pass band of the filter 2 employed for noise reduction, but a problem arises therefrom that there is also narrowed the frequency band of the signal itself received from the input terminal and delivered from the output terminal with addition of reverberative echo effect.
In an attempt to solve the above problem, there is adopted, in the analog type apparatus of FIGS. 2 and 3, a method of selectively setting a high clock frequency and increasing the number of stages of delay means such as BBDs.
Meanwhile in the digital type apparatus of FIGS. 4 to 6, there is adopted a method of setting a high sampling frequency or enhancing the resolution of both the A-D converter and the D-A converter. Particularly in the case of employing an oversampling A-D converter, it is customary to adopt a method which reduces any noise in the band by setting a high sampling frequency and enhancing the resolution of the A-D converter.
However, in either the analog or digital type, it becomes necessary to increase the number of stages of delay means and to enlarge the scale thereof for setting a long delay time by any of the methods mentioned above.
For example, relative to the required frequency band f.sub.B, the sampling frequency fs needs to satisfy the following condition on the basis of the sampling theorem. EQU f.sub.s &gt;2.multidot.f.sub.b ( 1)
And there exists the following relationship between the delay time .tau. per stage of the delay means and the sampling frequency f.sub.s. EQU .tau.=1/f.sub.s ( 2)
Therefore, in relation also to the required delay time T, the number n of required stages of the delay means is expressed as EQU n=T/.tau.=T.f.sub.B &gt;2T.f.sub.s ( 3)
For example, under the conditions of f.sub.B =20 (kHz) and T=100 (msec), EQU n&gt;4000 (4)
If each of the A-D converter and the D-A converter has a 16-bit resolution, the required capacity N of the memory is expressed as EQU N&gt;4000.multidot.16=64000 (bits) (5)
Even in the case of using an oversampling A-D converter, it becomes necessary to employ a memory of a great capacity substantially equivalent to the above.
Consequently, for satisfying the requirements relative to the signal frequency band, the S/N and the echo time in the conventional echo generating apparatus of the prior art, there exists a problem of increase in the production cost of the system.
If the delay time T is shortened and the gain of the feedback to the calculator is set to a great value, a long echo time may be achieved in the cyclic circuit configuration of FIG. 2 or 4. Practically, however, the following problems are raised if the delay time T is shortened in excess.
(1) The sound quality is distorted like flutter echo which is difficult to hear. PA1 (2) The operation is rendered unstable, including that oscillation is caused even by a slight variation of the feedback gain.
Accordingly, it becomes impossible to set a sufficiently high sampling frequency f.sub.s. Since the band of the filter 2 needs to be longer than half the sampling frequency f.sub.s, the band width of the output signal is rendered narrow to eventually fail in attaining auditory satisfaction.
FIGS. 7 to 9 show some more conventional echo generating apparatus of the related art.
In the conventional example of FIG. 7, an audio signal received from an input terminal 61 is processed via a mixer 62, a filter 63, a bucket brigade device (BDD) 67 serving as an analog delay element, and a filter 64, and then is delivered from an output terminal 65. Simultaneously the output of the filter 64 is fed back to the mixer 62 via a feedback gain control resistor 66, whereby reverberative echo effect is added to the input audio signal.
The BBD 67 is driven by a clock signal obtained from a clock generator 68, so as to delay the input audio signal.
In the next conventional echo generating apparatus of FIG. 8, an audio signal received from an input terminal 71 is supplied via a filter 73 to an A-D converter 74 so as to be digitized, and the resultant digital signal is converted to an analog signal by a D-A converter 76 after being delayed by a memory circuit 75. The analog signal thus obtained is delivered from an output terminal 80 via a filter 79, while the output of the filter 79 is fed back to a mixer 72 via a feedback gain control resistor 81, whereby reverberative echo effect is added to the input audio signal.
Timing control is executed by a timing circuit 78 for each of the A-D converter 74, the memory circuit 75 and the D-A converter 76.
Another conventional echo generating apparatus of FIG. 9 is substantially the same in fundamental configuration as the above-described example of FIG. 8. As shown, this apparatus comprises an amplifier 104, a mixer 92, a filter 93, an A-D converter 94, a memory circuit 95, a D-A converter 96, a filter 99 and a buffer amplifier 105. The entire circuit blocks are constituted by the CMOS process and are so integrated as to form a single chip.
In this conventional example, the output of the filter 99 is fed back to the mixer 92 via an external feedback gain control resistor 103 and an input terminal 106 so as to be mixed by a mixer 101 with the input audio signal delivered via the buffer amplifier 105 and the output terminal 109, and then the mixed signal is delivered from an output terminal 110.
However, in the conventional example of FIG. 7 where the BBD needs to be manufactured in the form of an individual chip, a great number of chips are required to constitute the entire apparatus and, due to the necessity of many external elements to be connected to the apparatus, some problems are unavoidable including difficulties in reducing the occupied area and curtailing the production cost. Furthermore, since the amplitude of the analog signal transmitted through the BBD is generally smaller than the amplitude of the clock signal, the S/N is prone to be lowered by the clock noise.
Also in the next conventional example of FIG. 8, the same problems as the above are existent since the A-D converter, the memory circuit and the D-A converter are formed normally in individual chips.
Although such problems may be solved in the last conventional example of FIG. 9 where the component circuits are formed into a single chip, another problem still remains unsolved that, as the input and output characteristics of the A-D converter and the D-A converter are generally dependent upon the supply voltage, some variations in the gain, the dynamic range and the S/N occur due to the variations in the supply voltage.